Don’t get me wrong, RVN is actually my favorite Crypto… But…

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Don’t get me wrong, RVN is actually my favorite Crypto… But…

I dislike that you use the term Asic Resistant. It's dishonest in my book. It's not Asic Resistant, no one's ever cared to make one yet. So far, I haven't found a single shred of evidence that will make something Asic Resistant / Proof. Because no one really cares. So, I spent the last 3 months designing one. Then I decided to maybe dabble in creating my own. There are a thousand things I dislike that all Cryptos do. The first is giving away 60% of your TOTAL SUPPLY in the first 4 years (out of a 60 year goal.) It will eventually lose the interest of miners and then there goes your infrastructure. But If you don't understand VDHL, or Verilog, along with BGAs and IC chips, you're never going to make an FPGA or ASIC.

This is a simple hardware design×1600/i/73055/products/2018-08-07T07%3A39%3A50.234Z-schematic.png

This is a simple to medium

And when I say simple. I mean it doesn't take 8 months to complete. And this is just the layout.

There is a huge amount of work that goes into designing an asic. And the people who know how to do this professionally, don't have any issues making money.

But, if you don't understand how they work, how can you even say Asic Resistant? I've studied your algorithm. It's not. Not even close. I can slap some IC chips on an Asic in 5 minutes. It's the easiest thing to do. Your DAG does nothing but thwart miners while adding a slight, SLIGHT inconvenience to an Asic or FPGA designer. You can get 128MB DDR3 IC RIMM CHIPs for $1 a piece. You know I can just put on as many as I want, right? It's the weakest defense against ASICs.

You can change your Algorithm every 6 months, but you're just going to piss off your ENTIRE community when you do. Your algorithm is nothing special. Wasteful, but that's just Crypto.

You should have asked a hardware designer a way to thwart an Asic. But we're a snobby kind. We prefer people work for their solution. There is a group of people who make FPGAs solutions (which has the memory issues taken care of because of new PCI protocols, Ultra RAM, DDRAM, etc.) Who just sell the code for $50. If you find someone selling it for that price, it's either a scam or it's an embedded software design which is going to ROYALY suck. It never made sense to me. Why the hell would people development an Asic and then SELL IT? they're just raising the difficulty and they could make an even BIGGER fortune mining it themselves. Horrible businessmen.

Anyway. If you read this far and you want to check out a Crypto I'm developing. You can go to r/Cytogon.

That's Seh-toghun. Not Cite O Gone like a toddler would say. 😒😂

But it's going to be very Asic PROOF, with most of it open source except for the code that makes it Asic proof. That will be closed sourced (and yes, you can have closed source on top of open source) and only shared with a few miner builds, but this will have it's own dedicated mining software so that it can take advantage of CUDA, Tensor, CPU, and AMDs of all kinds. The goal is to have an GPU with Tensor Cores be 2.5x faster than just GPU with only CUDA/OpenCL, and those will be 2x faster than a CPU of equal caliber. (Or approximately)

Example: a 4c 8t 3.4GHz 9th gen processor would be twice as slow as it's equivalent which I would argue is a NVIDIA 1050 ti.

Since Tensor Cores are the most expensive, the algorithm will favor the (FP16)(FP16) + FP32 = FP16 Tensor Matrix. It just needs to be designed to have a variable checksums depending on the level so that an A100 doesn't accidentally get approved to do 12 trillion hashes 😂

But follow r/Cytogon and I'll post there very seldom. If you'd like to help out. Come chat. If you have an idea. Come chat. I think Crypto needs more involvement in it's creation from the community. We all have something we don't like about Crypto. We all have ideas. I want Cytogon to be very community based.

submitted by /u/Alehti
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